PLL_ENABLE=Val_0x0, CLK_GEN_SELECT=Val_0x0, SD_CLK_EN=Val_0x0, INTERNAL_CLK_EN=Val_0x0, INTERNAL_CLK_STABLE=Val_0x0
Clock Control Register
| INTERNAL_CLK_EN | Internal Clock Enable. This bit is set to 0x0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host Controller must stop its internal clock to enter a very low power state. However, registers can still be read and written to. Note: If this bit is not used to control the internal clock (base clock and master clock), it is recommended to set it to 0x1. 0 (Val_0x0): Stop 1 (Val_0x1): Oscillate |
| INTERNAL_CLK_STABLE | Internal Clock Stable. This bit enables the Host Driver to check the clock stability twice after the SDMMC_CLK_CTRL_R[INTERNAL_CLK_EN] bit is set and after both INTERNAL_CLK_EN and PLL_ENABLE bits are set. 0 (Val_0x0): Not ready 1 (Val_0x1): Ready |
| SD_CLK_EN | SD or eMMC Clock Enable. This bit stops the SD_CLK when is set to 0x0. The FREQ_SEL bit field can be changed when this bit is set to 0x0. 0 (Val_0x0): Disable providing SD_CLK 1 (Val_0x1): Enable providing SD_CLK |
| PLL_ENABLE | PLL Enable. This bit is used to activate the PLL (applicable when the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x1). When the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x0, the INTERNAL_CLK_EN bit may be used to activate PLL. Note: If this bit is not used to active the PLL when the SDMMC_HOST_CTRL2_R[HOST_VER4_ENABLE] = 0x1, it is recommended to set it to 0x1. 0 (Val_0x0): PLL is in low power mode 1 (Val_0x1): PLL is enabled |
| CLK_GEN_SELECT | Clock Generator Select. This bit is used to select the clock generator mode in SD_CLK Frequency Select-FREQ_SEL bit. If the SDMMC_HOST_CTRL2_R[PRESET_VAL_ENABLE] = 0x0, this bit is set by the Host Driver. If the SDMMC_HOST_CTRL2_R[PRESET_VAL_ENABLE] = 0x1, this bit is automatically set to a value specified in one of the Preset Value registers. 0 (Val_0x0): Divided clock mode 1 (Val_0x1): Programmable clock mode |
| UPPER_FREQ_SEL | These bits specify the upper 2 bits of 10-bit SD_CLK Frequency Select control (FREQ_SEL bit field). |
| FREQ_SEL | SD_CLK Frequency Select. These bits are used to select the frequency of the SD_CLK signal. These bits depend on setting of the SDMMC_HOST_CTRL2_R[PRESET_VAL_ENABLE] bit. If the SDMMC_HOST_CTRL2_R[PRESET_VAL_ENABLE] = 0x0, these bits are set by the Host Driver. If the SDMMC_HOST_CTRL2_R[PRESET_VAL_ENABLE] = 0x1, these bits are automatically set to a value specified in one of the Preset Value register. 10-bit Divided Clock Mode: 0x000: Base clock 0x001: 1/2 Divided clock 0x002: 1/4 Divided clock … N: 1/2N Divided clock … 0x3FF: 1/2046 Divided clock Programmable Clock mode (enables the Host System to select a fine grain SD clock frequency): 0x000: Base clock x M 0x001: Base clock x M/2 0x002: Base clock x M/3 … N-1: Base clock x M/N … 0x3FF: Base clock x M/1024 |